Fail-safe FPGA design features for high-reliability systems

FPGAs have become a ubiquitous part of today´s processing technology. Their use has grown from traditional glue logic interfaces of the past to the most advanced information processing systems used by core Internet routers and high-performance computing systems. What remains common throughout this evolution is the desire to integrate more functionality in less space while using less power and at a lower cost. High-reliability system design has experienced a similar need to reduce system size, power, and cost while maintaining expected reliability. Traditionally, these systems designs have approached reliability through redundancy. This redundancy manifests itself though increased component count, logic size, system power, and cost. These requirements and attributes are shared by other system design areas, including information assurance, avionics, and industrial safety systems. This paper provides an overview of these design areas with a focus on the ability to securely partition redundant logic used in high-assurance designs by the cryptography community. It also describes a new method of collapsing the established high-reliability redundant design methodologies into a single-chip FPGA-based architecture, and presents an overview of the design flow used for development of the FPGA separation features.