DocumentCode :
3084216
Title :
LFSR Reseeding with Irreducible Polynomials
Author :
Udar, Snehal ; Kagaris, Dimitri
Author_Institution :
Southern Illinois Univ. at Carbondale, Carbondale
fYear :
2007
fDate :
8-11 July 2007
Firstpage :
293
Lastpage :
298
Abstract :
We propose an innovative scheme for LFSR re- seeding based on the efficient generation of the seeds of any non-primitive irreducible polynomial. The scheme has very small hardware overhead irrespective of the number of seeds and guarantees that the generation of the pattern subsequence from each seed is disjoint. Experimental results demonstrate the potential of the mechanism for pseudorandom test pattern generation in a parallel chain test-per-scan environment.
Keywords :
automatic test pattern generation; logic testing; polynomials; shift registers; LFSR reseeding; irreducible polynomials; pseudorandom test pattern generation; AC generators; Built-in self-test; Circuit faults; Circuit testing; Hardware; Linear feedback shift registers; Polynomials; Read only memory; Test pattern generators; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2007. IOLTS 07. 13th IEEE International
Conference_Location :
Crete
Print_ISBN :
0-7695-2918-6
Type :
conf
DOI :
10.1109/IOLTS.2007.43
Filename :
4274869
Link To Document :
بازگشت