Title :
An improved bang-bang phase detector for clock and data recovery applications
Author :
Ramezani, Mehrdad ; Salama, C Andre T.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
A low power fully integrated PLL-based 5 Gb/s NRZ clock and data recovery circuit was successfully implemented in a 0.18 μm CMOS process. A novel bang-bang phase detector, used in the implementation, resulted in improved jitter performance compared to conventional bang-bang detectors. Differential topologies were used for the charge-pump and VCO circuits to reduce the design sensitivity to power supply noise. The maximum measured clock jitter from a 223-1 pseudorandom bit stream (PRBS) input data was less than 4.8 ps rms. The total power dissipation was less than 80 mW from a 1.8 V supply
Keywords :
CMOS integrated circuits; low-power electronics; phase detectors; phase locked loops; synchronisation; timing jitter; voltage-controlled oscillators; 0.18 micron; 1.8 mV; 5 Gbit/s; 80 mW; CMOS chip; NRZ signal; PRBS signal; bang-bang phase detector; charge pump; clock and data recovery circuit; clock jitter; differential VCO; low-power PLL; CMOS process; Charge pumps; Circuit topology; Clocks; Detectors; Jitter; Optical signal processing; Phase detection; Power supplies; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921956
