Cu dual damascene for advanced metallisation (0.18 μm and beyond)

A review of specific steps performed during integration of Cu metallisation in a multilevel dual damascene architecture has been made. Several steps are identified as crucial processes for copper integration and a complete optimisation should include dual damascene architecture, barrier material and deposition process, copper deposition process and chemical mechanical polishing (CMP). All of these aspects are reviewed, illustrated with examples and discussed, including comparison of several dual damascene architectures, comparison of barrier material performance both for PVD and CVD processes, comparison of Cu ECD and Cu CVD approaches with a look at the complementary aspects of these methods. Copper contamination issues, a major concern for introduction of copper metallisation, are addressed in detail. On active devices, several barrier materials have been claimed as being efficient against copper diffusion. However, during process integration, contamination issues are faced before deposition of the barrier layers. Heavy contamination can occur either during Cu CMP or during dielectric etching and via opening on top of contacted copper lines. These residues concentrated at the dielectric surface would be effective sources for current leakage and shorts between interconnection lines. Several cleaning solutions to remove metal contamination are reviewed and their efficiencies compared