Title :
Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM
Author :
Chang-Hong Shen ; Jia-Min Shieh ; Tsung-Ta Wu ; Wen-Hsien Huang ; Chih-Chao Yang ; Chih-Jen Wan ; Chein-Din Lin ; Hsing-Hsiang Wang ; Bo-Yuan Chen ; Guo-Wei Huang ; Yu-Chung Lien ; Wong, Simon ; Chieh Wang ; Yin-Chieh Lai ; Chien-Fu Chen ; Meng-Fan Chang
Author_Institution :
Nat. Nano Device Labs., Hsinchu, Taiwan
Abstract :
For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.
Keywords :
MOS logic circuits; MOS memory circuits; SRAM chips; elemental semiconductors; logic circuits; silicon; three-dimensional integrated circuits; 6T SRAM; NVM circuits; Si; UTB MOSFET; intelligent mobile device; interlayer dielectric; logic circuits; monolithic 3D IC; monolithic 3D chip; plasma-MONOS NVM; size 20 nm; static noise margin; time 3 ps; time 500 ns; ultrathin-body MOSFET; voltage 280 mV; CMOS integrated circuits; Inverters; MOSFET; Nonvolatile memory; Random access memory; Silicon; Three-dimensional displays;
Conference_Titel :
Electron Devices Meeting (IEDM), 2013 IEEE International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.2013.6724593
