Capacitor-area and power-consumption optimization of high-order Δ-Σ modulators

A design methodology for the power-consumption optimization of high-order high-resolution single-bit SC-type Δ-Σ modulators is described. The main reasons for the power consumption are determined and appropriate steps for its reduction are proposed. The algorithm is coded in MATLAB and gives the unit capacitor size of each integrator stage for an arbitrary topology and the required specification of each opamp used in the integrator to achieve the required S/N ratio, minimize the power consumption and the silicon area and preserve matching accuracy. A 5th-order modulator was built and the results prove the effectiveness of the approach