Author :
Guo, Wenyong ; Moroz, Victor ; Van der Plas, G. ; Choi, Michael ; Redolfi, A. ; Smith, Lee ; Eneman, Geert ; Van Huylenbroeck, Stefaan ; Su, P.D. ; Ivankovic, A. ; De Wachter, B. ; Debusschere, I. ; Croes, Kristof ; De Wolf, Ingrid ; Mercha, Abdelkarim ;
Abstract :
This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; three-dimensional integrated circuits; transport processes; Cu; FinFET device; FinFET technology; TCAD subband modeling; TSV integration; TSV proximity induced keep out zone; bulk FinFET CMOS technology; carrier transport; copper through silicon via; Analytical models; Data models; FinFETs; Semiconductor device modeling; Silicon; Stress; Through-silicon vias;
