Design and implementation of algorithm for DES cryptanalysis

With the advent of low cost Field Programmable Gate Arrays (FPGA´s), building special purpose hardware for computationally intensive applications has now become possible. Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. This paper presents the design for Hardware implementation of Data Encryption Standard (DES) cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Iterative and Loop unrolled DES architecture are implemented. The aim of this work is to make cryptanalysis faster and better.