A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications

Author

Shangquan, Liang ; Minglun, Gao ; Yongsheng, Yin ; Honghui, Deng

Author_Institution

Hefei Univ. of Technol., Hefei

fYear

2008

fDate

23-25 Jan. 2008

Firstpage

111

Lastpage

114

Abstract

A 14-bit, 320MSPS digital-to-analog converter is designed for high-speed applications. Considering the trade-off among linearity, dynamic performance, chip area, and power dissipation, the proposed DAC employs 5+4+5 segmented structure. The paper focuses on the design of several key circuits, and presents the experiment results (DNL=plusmn2.0LSB , INL=plusmn2.7LSB , SFDR=72.6dB @ f_data=320MSPS, f_out= 4.375 MHz) based on the SMIC 0.35 mum mixed signal 2P3M CMOS process model. The chip has been fabricated in the SMIC 3.3 V technology with an active area of 2.6times2.6 mm².

Keywords

CMOS analogue integrated circuits; CMOS digital integrated circuits; digital-analogue conversion; CMOS process model; DAC; high-speed applications; mixed signal; power dissipation; segmented current-steering D-A converter; CMOS technology; Communication switching; Decoding; Digital-analog conversion; Electronic equipment testing; Linearity; Power dissipation; Switches; Switching circuits; Very large scale integration; current switch driving circuit; pseudorandom switching sequence; segmented current-steering; unit current-cell;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on

Conference_Location

Hong Kong

Print_ISBN

978-0-7695-3110-6

Type

conf

DOI

10.1109/DELTA.2008.43

Filename

4459521