Designing self-checking FPGAs through error detection codes

Presents an approach for adapting sound techniques for designing Totally Self-Checking (TSC) combinational circuits based on error detection codes developed in the past for ASIC platforms to FPGA architectures. The attention is focused on the constrained synthesis of the logic functions that must guarantee that each possible fault produces only observable errors with respect to the adopted error detection code. An experimental framework has been setup to evaluate the effectiveness of Concurrent Error Detection (CED) design methodologies to a set of benchmark circuits. Results show that the physical implementation of the functionally TSC network onto an FPGA does not maintain the desired properties, requiring a post synthesis modification of the obtained network in order to achieve the pursued fault coverage. As a consequence, specific FPGA techniques for both fault analysis and CED design methodologies will have to be investigated.