DocumentCode :
3090829
Title :
A fault hypothesis study on the TTP/C using VHDL-based and pin-level fault injection techniques
Author :
Blanc, S. ; Gracia, J. ; Gil, P.J.
Author_Institution :
Univ. Politecnica de Valencia, Spain
fYear :
2002
fDate :
2002
Firstpage :
254
Lastpage :
262
Abstract :
Fault injection techniques are frequently used for validating dependable systems. VHDL-based techniques are good resources that support fault injection with many advantages such as a high level of accessibility, controllability and precision. This paper presents the results obtained with a VHDL-based tool (VFIT) injecting single and multiple faults at pin-level in a TTP/C model. The study is focused on the fault hypothesis of a modelled communications protocol based on the Time-Triggered Architecture. Results are analysed and compared with the experiments carried out in the real prototyped system with a pin-level fault injection tool (AFIT). Conclusions strengthen the usability of VHDL-based fault injection tools and reveal technique weaknesses.
Keywords :
VLSI; fault simulation; hardware description languages; protocols; time division multiple access; transients; TTP/C model; VFIT; VHDL-based fault injection techniques; accessibility; controllability; fault hypothesis; fault hypothesis study; multiple faults; pin-level fault injection techniques; single faults; time-triggered architecture; Access protocols; Communication system control; Controllability; Fault tolerant systems; Gas insulated transmission lines; Hardware design languages; Prototypes; Real time systems; Time division multiple access; Usability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on
ISSN :
1550-5774
Print_ISBN :
0-7695-1831-1
Type :
conf
DOI :
10.1109/DFTVS.2002.1173522
Filename :
1173522
Link To Document :
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