Modeling of FPGA local/global interconnect resources and derivation of minimal test configurations

This paper addresses the issues of automating the derivation of test configurations (TCs) for both local and global interconnect of SRAM-based FPGAs. We model FPGA interconnect and their test requirements using adjacency graphs and obtain the minimal or near minimal TO by solving the graph coloring problem, using a modified greedy algorithm. We apply the proposed modeling and TC derivation method to the Xilinx XC4000 FPGA. A set of minimal TCs was derived automatically. The proposed method is applicable to FPGAs of various interconnect structures and sizes, and supports distinctive test logic.