Title :
Allocation of multiport memories for hierarchical data streams
Author :
Lippens, P.E.R. ; Van Meerbergen, J.L. ; Verhaegh, W.F.J. ; van der Werf, A.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
A multiport memory allocation problem for hierarchical, i.e. multi-dimensional, data streams is described. Memory allocation techniques are used in high level synthesis for foreground and background memory allocation, the design of data format converters, and the design of synchronous inter-processor communication hardware. The techniques presented in this paper differ from other approaches in the sense that data streams are considered to be design entities and are not expanded to individual samples. A formal model for hierarchical data streams is given and a memory allocation algorithm is presented. The algorithm comprises two steps: data routing and assignment of signal delays to memories. A number of sub-problems are formulated as ILP programs. In the presented form, the allocation algorithm only considers interconnect costs, but memory size and other cost factors can be taken into account. The presented work is implemented in the memory allocation tool MEDEA which is part of the PHIDEO synthesis system.
Keywords :
storage allocation; MEDEA; PHIDEO synthesis system; data format converters; data routing; design entities; hierarchical data streams; high level synthesis; integer linear programming; interconnect costs; memory size; multidimensional data streams; multiport memory allocation; signal delay assignment; synchronous inter-processor communication hardware; Clocks; Costs; Delay; Hardware; High level synthesis; Laboratories; Pipeline processing; Registers; Routing; Signal synthesis;
Conference_Titel :
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-4490-7
DOI :
10.1109/ICCAD.1993.580169