Adaptive test scheduling in SoC´s by dynamic partitioning

Author

Zhao, Dan ; Upadhyaya, Shambhu

Author_Institution

Dept. of Comput. Sci. & Eng., State Univ. of New York, USA

fYear

2002

fDate

2002

Firstpage

334

Lastpage

342

Abstract

In this paper, we present a novel adaptive scheduling algorithm for testing embedded core-based SoC´s. Tests are scheduled in a way that dynamically partitions and allocates the tests, consequently constructing and updating a set of dynamically partitioned power constrained concurrent test sets, and ultimately reducing the test application time. A simulation study shows the productivity gained by our new approach.

Keywords

VLSI; integrated circuit testing; scheduling; system-on-chip; SoC testing; adaptive scheduling algorithm; concurrent test sets; dynamically partitioned test sets; embedded core-based SoCs; power constrained test sets; test application time reduction; Adaptive scheduling; Circuit testing; Costs; Dynamic scheduling; Energy consumption; Fault detection; Job shop scheduling; Parallel processing; Processor scheduling; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-1831-1

Type

conf

DOI

10.1109/DFTVS.2002.1173530

Filename

1173530

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3091003