Title :
Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec
Author :
Gao, Lijun ; Parhi, Keshnb K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier con be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(2m) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier
Keywords :
Galois fields; Reed-Solomon codes; VLSI; application specific integrated circuits; codecs; integrated circuit design; low-power electronics; multiplying circuits; GF(2m); Reed-Solomon codec; circuit design; custom VLSI architecture; delay; finite field multiplier; irregular balanced-tree parallel multiplier; latency; logic structure; low-power design; physical mapping; power consumption; Arithmetic; Codecs; Delay; Energy consumption; Galois fields; Iterative algorithms; Iterative decoding; Pipelines; Reed-Solomon codes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.922302