DocumentCode :
3091632
Title :
A Prevenient Voltage Stress Test Method for High Density Memory
Author :
Yim, Jongsoo ; Kim, Gunbae ; Nam, Incheol ; Son, Sangki ; Lim, Jonghyoung ; Lee, Hwacheol ; Kang, Sangseok ; Kwak, Byungheon ; Lee, Jinseok ; Kang, Sungho
Author_Institution :
Yonsei Univ., Seoul
fYear :
2008
fDate :
23-25 Jan. 2008
Firstpage :
516
Lastpage :
520
Abstract :
The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).
Keywords :
DRAM chips; integrated circuit reliability; integrated circuit testing; integrated circuit yield; nanotechnology; transistor circuits; burn-in test; early life failure rates; nanometer technology; prevenient voltage stress test; product reliability test; thin gate oxide transistors; voltage ramp stress; Breakdown voltage; Circuit testing; Degradation; Electronic equipment testing; Life estimation; Packaging; Random access memory; Stress; Temperature; Voltage control; acceleration factor; burn-in test; constant voltage stress; junction temperature; reliability; voltage ramp stress; voltage stress test;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on
Conference_Location :
Hong Kong
Print_ISBN :
978-0-7695-3110-6
Type :
conf
DOI :
10.1109/DELTA.2008.93
Filename :
4459605
Link To Document :
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