DocumentCode :
309220
Title :
Prefetching by self-contained variables-a generalization from array to recursive data structures
Author :
Wai-wai, Chang ; Chi-hung, Chi
Author_Institution :
Dept. of Inf. Syst. & Comput. Sci., Nat. Univ. of Singapore, Singapore
fYear :
1997
fDate :
17-21 Mar 1997
Firstpage :
225
Lastpage :
232
Abstract :
Data prefetching has proven to be effective in hiding memory latency from the program execution time. Most current data prefetching schemes are targeted only for array references with constant strides; for array references with non-constant strides, they lose most of their effectiveness. In this paper, we propose a novel data prefetching scheme, based on a property called the self-containedness of variables, which is widely available in most loop-rich applications. We observed that the update pattern of a self-contained variable in a loop can be accurately predicted. The predicated value can then be used for accurate data prefetching if the variable is the only loop-variant component of an address expression in a memory access instruction. With suitable hardware support, this scheme can be used to prefetch data from recursive data structures in additional to array elements. Moreover, the coverage of this scheme is highly selectable. It can be customized easily to fit the cost-performance requirements of different processors that are designed for different applications
Keywords :
arrays; data structures; program control structures; storage management; address expression; array data structures; array references; customizability; data prefetching scheme; hardware support; loop-rich applications; loop-variant component; memory access instruction; memory latency hiding; nonconstant strides; processor cost-performance requirements; program execution time; recursive data structures; selectable coverage; self-contained variables; variable update pattern prediction; variables self-containedness; Computer science; Data structures; Delay; Hardware; High level languages; Information systems; Prefetching; Program processors; Programming profession; Reduced instruction set computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Algorithms/Architecture Synthesis, 1997. Proceedings., Second Aizu International Symposium
Conference_Location :
Aizu-Wakamatsu
Print_ISBN :
0-8186-7870-4
Type :
conf
DOI :
10.1109/AISPAS.1997.581667
Filename :
581667
Link To Document :
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