DocumentCode :
3092946
Title :
NBTI-aware statistical circuit delay assessment
Author :
Vaidyanathan, Balaji ; Oates, Anthony S. ; Xie, Yuan ; Wang, Yu
Author_Institution :
Taiwan Semicond. Manuf. Co. Ltd., Hsinchu
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
13
Lastpage :
18
Abstract :
This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread.
Keywords :
CMOS integrated circuits; delays; integrated circuit reliability; NBTI aging effect; circuit NBTI mitigation techniques; negative bias temperature instability; product delay spread; reliability; statistical PMOS NBTI DC-lifetime variability; statistical circuit delay distribution; Aging; CMOS technology; Circuits; Degradation; Delay effects; Equations; Niobium compounds; Stress; Titanium compounds; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810263
Filename :
4810263
Link To Document :
بازگشت