Hybrid neural model for automatic test pattern generation

In this paper, an original strategy for automatic test pattern generation (ATPG) for synchronous sequential circuits is presented. This problem is known to be a difficult and time-consuming task. Different approaches based on Hopfield´s neural nets have been proposed recently to exploit massively parallel computing. These approaches involve the development of algorithms which allow an energy function associated with the neural net to be minimized. This net represents the behavior of a digital circuit and necessary conditions for fault activation. In this paper, we propose a new neural hybrid model for circuit modeling. This model allows information given by the structure and behavior of digital gates to be used. As a result, new minimization algorithms are presented. The first results obtained from the ISCAS´85 and the combinational part of ISCAS´89 benchmarks are promising