Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization

A novel phenomenological inverter delay model is presented. The model focuses on capturing the percentage delay change as a function of gate length change (i.e., bias) over a wide, practical range of input slews and output capacitances that are typically used in library characterization. The model is derived based on physical device equations with empirical fitting parameters for improved accuracy. In the model, a physically based parameter, V_sc, is introduced that represents the output voltage value at the end of the short circuit region. Fitting results for inverters of five different drive strengths show an average accuracy of 0.24% and 0.37% with respect to HSPICE simulations for cell rise and fall delays, respectively. Applications of this delay model include library characterization and optimal gate length biasing during physical design implementation and circuit optimization.