Architectures for high performance digital control processors

This paper reports on a research project which is developing algorithms and architectures for a control system processor (CSP). The design considerations given suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used as an example to illustrate some of the issues. The problem of an optimal realization of digital controllers taking into account finite wordlength issues is investigated within the framework of the delta (δ) operator formulation, which provides improved numerical capabilities with high sampling rate, fixed point computations and improved I/O requirements