DocumentCode :
3095029
Title :
A single chip architecture for multiprocessor DSP
Author :
Brown, C.I. ; Thacker, N.A. ; Yates, R.B.
Author_Institution :
Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
fYear :
1995
fDate :
34850
Firstpage :
42522
Lastpage :
42527
Abstract :
This paper describes a single chip multiprocessor for sparse matrix multiplications that efficiently exploits parallelism. The device uses cache RAM to minimise the memory bandwidth required. Access to the cache RAM is restricted to the external system so that the processors cannot cause inconsistencies in the data held in the caches. The processors are connected to the cache RAMs directly. Many multiprocessors use a cross bar switch to connect the processors and the cache RAM, but this has been shown to be inefficient and unnecessary. Mapping algorithms onto the system has been demonstrated using the wavelet transform
Keywords :
CMOS digital integrated circuits; cache storage; digital signal processing chips; matrix multiplication; multiprocessing systems; parallel architectures; random-access storage; sparse matrices; wavelet transforms; CMOS process; cache RAM; cross bar switch; mapping algorithms; memory bandwidth; multiprocessor DSP; parallelism; single chip architecture; sparse matrix multiplications; wavelet transform;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures, IEE Colloquium on (Digest No.1995/116)
Conference_Location :
London
Type :
conf
DOI :
10.1049/ic:19950779
Filename :
405158
Link To Document :
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