A novel architecture of a reconfigurable radio processor for implementing different modulation schemes

Designing high performance Software Defined Radio (SDR) with low power and flexibility is a major challenge. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently dynamically reconfigurable FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions efficiently. Some FPGAs offer MAC (multiply and accumulate) units which the basic units for signal processing functions. Since basic intention of an SDR is to implement different modulation / demodulation schemes, basic building blocks for such schemes are signal processing functions and FPGAs have become an important component for implementing these. However, the effectiveness of such an approach with respect to cost, performance and flexibility need to be examined. Keeping these issues in view, this paper proposes a new flexible architecture Radio-Processor (RP) for designing SDR, examines the feasibility of efficient implementation of the such a processor using state-of-the-art FPGAs and finally suggests an ASIC implementation.