DocumentCode
3095151
Title
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme
Author
Okumura, Shunsuke ; Iguchi, Yusuke ; Yoshimoto, Shusuke ; Fujiwara, Hidehiro ; Noguchi, Hiroki ; Nii, Koji ; Kawaguchi, Hiroshi ; Yoshimoto, Masahiko
Author_Institution
Kobe Univ., Kobe
fYear
2009
fDate
16-18 March 2009
Firstpage
659
Lastpage
663
Abstract
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement, we confirmed that the proposed 128-kb SRAM works at 0.56 V.
Keywords
SRAM chips; low-power electronics; SRAM cell; column line assist scheme; half selection problem; storage capacity 128 Kbit; voltage 0.56 V; write margin degradation; Degradation; Integrated circuit interconnections; Logic; Low voltage; MOSFETs; Random access memory; Read-write memory; Threshold voltage; SRAM; low-voltage operation;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-2952-3
Electronic_ISBN
978-1-4244-2953-0
Type
conf
DOI
10.1109/ISQED.2009.4810372
Filename
4810372
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