Novel architecture of EBC for JPEG2000

The paper presents a novel architecture of EBC (embedded block coding) for JPEG2000. It presents three speed-up methods: bit-plane parallelization, three stage pipelined architecture of context formation block and three stage pipelined architecture of MQ encoder block. The proposed design would consequently enhance the throughput and reduce latency, enabling high speed compression. The synthesis and implementation of the design was done on 0.13μ technology using Cadence RTL compiler.