Design of multi-bit SET adder and its fault simulation

The paper describes an efficient approach towards the simulation of a multi-bit adder through single electron technology based on the concept of binary decision diagram (BDD). Single electron transistor (SET) technology is one of the future technology based on ultra-low power dissipation and reduced Coulomb oscillation. Here, we describe an algorithm for the construction of a multi-bit adder followed by generation of stuck-at faults at different nodes of different levels of the adder. The algorithm also simulates the detection of a faulty level. In this paper, we demonstrate the construction procedure of an 8 bit full-adder and verify the design by means of simulation. This approach provides a novel approach towards simulating full adder circuit and also its fault analysis.