Impact of SoC power management techniques on verification and testing

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power is a primary design criterion for bulk of the semiconductor designs now and a key reason behind the shift towards multicore designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. This implies that if voltage can be controlled to optimally meet the performance then there can be much to be gained in terms of power savings. In this tutorial, we look into the details of some of key power management techniques that leverage voltage as a handle: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi- Threshold CMOS (MTCMOS), and Active Body Bias (ABB). We look into their verification and testing implications. The use of above mentioned techniques also imply new challenges in validation of designs as new power states are created. We look into the characteristics of typical power states that exist in such designs and detail the techniques used in design validation. Techniques that leverage simulation, formal, and rule-based techniques are described in detail using examples. We make use of some of the latest mobile application-processor designs to aid explanation of these points. Power-aware testing is a major concern for designs that are leveraging voltage-based power management techniques and this poster will explore these challenges while providing some useful recommendations.