DocumentCode :
3095293
Title :
Markov source based test length optimized SCAN-BIST architecture
Author :
Farooqi, Aftab ; Gale, Richard O. ; Reddy, Sudhakar M. ; Nutter, Brian ; Monico, Chris
Author_Institution :
Dept of ECE, Texas Tech Univ., Lubbock, TX
fYear :
2009
fDate :
16-18 March 2009
Firstpage :
708
Lastpage :
713
Abstract :
Markov sources have been shown to be efficient pseudo-random pattern generators in SCAN-BIST. In this paper we give a new design for Markov sources. The new design first reduces the ATPG test set by removing the test cubes with low sampling probability and then produces test sequences based on a unique dynamic transition selection technique. Dynamic transition selection offers four transition options namely Markov source, inverted Markov source, fixed 0 and fixed 1. Experimental results show that the proposed design significantly reduces the test length to achieve 100% stuck-at fault coverage at the expense of a modest increase in the number of gates required to implement the test pattern generator.
Keywords :
Markov processes; built-in self test; integrated circuit design; random number generation; system-on-chip; Markov source; automatic test pattern generator; built-in-self-test; dynamic transition selection; inverted Markov source; pseudo-random pattern generators; system-on-chip devices; test length optimized SCAN-BIST architecture; Automatic test pattern generation; Built-in self-test; Circuit faults; Circuit testing; Clocks; Computer architecture; Logic testing; Polynomials; Sampling methods; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2952-3
Electronic_ISBN :
978-1-4244-2953-0
Type :
conf
DOI :
10.1109/ISQED.2009.4810380
Filename :
4810380
Link To Document :
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