A 4.9-dB NF 53.5–62-GHz micro-machined CMOS wideband LNA with small group-delay-variation

A 53.5-62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S₁₁) of -10.3~ -19.5 dB, output return loss (S₂₂) of -13.8~ -27.8 dB, forward gain (S₂₁) of 8.1~ 11.1 dB, and reverse isolation (S₁₂) of -49.9~ -60.2 dB over the 53.5-62-GHz-band. The minimum NF (NF_min) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S₂₁ (S_21-max) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NF_min of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.