DocumentCode :
3095470
Title :
A VLSI device for low bit rate coding
Author :
Brown, C.I. ; Thacker, N.A. ; Yates, R.B.
Author_Institution :
Dept. of Electron. Eng., Sheffield Univ., UK
fYear :
1995
fDate :
34856
Firstpage :
42491
Lastpage :
42496
Abstract :
The pitfalls of designing algorithms without reference to future hardware implications have been illustrated with respect to the implementation of H.261 and MPEG in VLSI systems. The wavelet transform has been shown to be better suited to hardware implementation than MPEG and H.261 by an order of magnitude and achieves higher compression ratios for a given quality. A new mapping onto a VLSI architecture of the wavelet transform is described. A single device can process images at a frame rate of over 30 QCIF frames per second (8 bit pixels) and the compressed bit stream on average 33 kbits per second at an image quality of 32 dB (PSNR)
Keywords :
VLSI; computational complexity; data compression; telecommunication standards; video coding; wavelet transforms; H.261; MPEG; VLSI architecture; VLSI device; compressed bit stream; compression ratio; frame rate; hardware implementation; low bit rate coding; wavelet transform;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Low Bit Image Coding, IEE Colloquium on
Conference_Location :
London
Type :
conf
DOI :
10.1049/ic:19950938
Filename :
405192
Link To Document :
بازگشت