Title :
A low power architecture design method based on DFG model
Author :
Chen, Tingting ; Zheying, L.
Author_Institution :
Coll. of Inf., Beijing Union Univ., Beijing, China
Abstract :
A low power architecture design method is brought forward by this paper based on DFG (Data Flow Graphic) model. Through this method, a DFG model is extracted from the logic model of a circuit or a system and is used to optimize the circuit architecture for reducing the power consumption of circuit. In this paper, the data transmission process of USB2.0 is taken as an example to prove the correctness of this low power architecture design method.
Keywords :
logic design; low-power electronics; DFG model; USB2.0; circuit architecture; circuit logic model; circuit power consumption; data flow graphic model; low power architecture design; Clocks; Combinational circuits; Data communication; Design methodology; Digital circuits; Energy consumption; Frequency synchronization; Logic circuits; Logic design; Power system modeling; DFG model; logic model; low power architecture design; time characteristic;
Conference_Titel :
Industrial Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference on
Conference_Location :
Taichung
Print_ISBN :
978-1-4244-5045-9
Electronic_ISBN :
978-1-4244-5046-6
DOI :
10.1109/ICIEA.2010.5515249
