A new protocol processing architecture for high-speed networks

Author

Matsuda, Takao ; Matsuda, Kazuhiro

Author_Institution

NTT Network Service Syst. Lab., Tokyo, Japan

Volume

2

fYear

1996

fDate

18-22 Nov 1996

Firstpage

798

Abstract

Conventional protocol processing has become a bottleneck in taking advantage of the opportunities presented by high-speed networks like ATM. Here, we describe a super high-speed protocol processor (SHiPP) architecture for protocol processing that increases speed by fine-grain parallel processing. The other feature of SHiPP is that it can be programmed by using content addressable memory (CAM) and field programmable gate arrays (FPGA). Experimentally, we apply SHiPP to the service specific connection oriented protocol (SSCOP). The SHIPP has achieved processing rates of about 4.3 μs per packet, about 28 times as fast as software implementations

Keywords

content-addressable storage; digital integrated circuits; field programmable gate arrays; parallel architectures; protocols; very high speed integrated circuits; SHiPP architecture; SSCOP; content addressable memory; field programmable gate arrays; fine-grain parallel processing; high-speed networks; processing rates; protocol processing architecture; service specific connection oriented protocol; super high-speed protocol processor architecture; Associative memory; Asynchronous transfer mode; CADCAM; Circuits; Computer aided manufacturing; Field programmable gate arrays; Hardware; High-speed networks; Parallel processing; Protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1996. GLOBECOM '96. 'Communications: The Key to Global Prosperity

Conference_Location

London

Print_ISBN

0-7803-3336-5

Type

conf

DOI

10.1109/GLOCOM.1996.585977

Filename

585977