Speed-up of input buffer asynchronous transfer mode switch by introducing of parallel read-out structure

A prototype first in first out (FIFO) input buffer asynchronous transfer mode (ATM) switch (element) is known as the architecture in which the transfer capacity is considerably limited and needs to be improved. The parallel readout structure, and three control rules for cyclic read-out (CRO) cell selection, parallel readout random (PROR) cell selection, and parallel readout maximum (PROM) queue selection for the structure are presented as novel switch architectures. The performance of the above switches are evaluated by simulation, and the results show that the parallel readout structure can give a drastic reduction of the buffer size. For the PROR and PROM switches, a large total hardware reduction can be achieved although a small hardware increment is necessary for parallel structure. The simulation results simultaneously show that the input buffer switches have a lower loss performance than that of the output buffer, keeping the delay almost equivalent to that of the output type buffer