Parametric ASIC-design by CADIC

Large ASIC´s often include regular blocks such as memories, arithmetic units and random logic. The design system CADIC enables a comfortable description of small and large blocks by a graphic interface. The paper describes experiences in the design of an ASIC chip implementing an efficiently testable floating point adder. By help of this example it is shown that CADIC combines both kinds of logic. Also it is possible to optimize the propagation delay of the floating point adder using specially adapted subcircuits