Yield enhancement and yield management of silicon foundries using Iddq “stress current signature”

This paper proposes a novel way of determining Iddq failure mechanisms by using a production test program, augmented with a voltage-stress-based current signature technique. In addition to a description of the test algorithm, the paper provides the methodology of data analysis, allowing meaningful conclusions regarding device quality and reliability. The stress current signature is validated by physical analysis using an innovative combination of techniques. This allows for fast, efficient, and successful investigation and failure analysis of common Iddq failures in the paradigm of IC manufacturing outsourcing