Characterization of NVSM gate stacks with ‘gridded’ capacitors

A shortened fabrication sequence and a method of testing, which is accomplished with a gridded capacitor structure is described for rapid characterisation of NVSM devices and conventional MOS transistor gate stacks. Specifically, hetero-insulator MINOS gate stacks on N+ gridded p-type silicon wafers is characterised. It is shown that gridded capacitor structure is a fast and inexpensive method to characterize electrically gate stacks for use in charge trapping NVSM and conventional transistors with a silicon substrate. The technique is also applicable to other substrate materials, particularly materials where adequate contact formation has been difficult to achieve.