Combined scheduling and data routing for programmable ASIC systems

Author

Hartmann, Ralf

Author_Institution

Dept. of Electr. Eng., Tech. Univ. of Munich, Germany

fYear

1992

fDate

16-19 Mar 1992

Firstpage

486

Lastpage

490

Abstract

A technique for mapping complex signal processing algorithms on programmable ASIC systems is presented. It integrates data routing into scheduling. An important problem is to cope with deadlocks during scheduling caused by limited register resources and fixed interconnect. An algorithm is presented which is able to generate a schedule for a broad class of architectures. It is integrated into a retargetable microcode compiler based on the Cathedral2nd framework. It was tested using an ISDN echo cancelling algorithm

Keywords

application specific integrated circuits; circuit CAD; microprogramming; network routing; program compilers; scheduling; signal processing; Cathedral2nd framework; ISDN echo cancelling algorithm; complex signal processing algorithms; data routing; deadlocks; fixed interconnect; limited register resources; programmable ASIC systems; retargetable microcode compiler; scheduling; Application specific integrated circuits; Hardware; ISDN; Processor scheduling; Routing; Scheduling algorithm; Signal design; Signal processing algorithms; System recovery; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1992. Proceedings., [3rd] European Conference on

Conference_Location

Brussels

Print_ISBN

0-8186-2645-3

Type

conf

DOI

10.1109/EDAC.1992.205983

Filename

205983