Title :
The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits
Author :
Roy, Kaushik ; Levitt, Marc E. ; Abraham, Jacob A.
Author_Institution :
Texas Instruments, Dallas, TX, USA
Abstract :
Due to the presence of multiple paths to charge or discharge the output node of a BiCMOS logic gate, many of the realistic open and short faults appear as rise or fall time delay faults without changing the functionality of the circuit. Based on circuit level faults, it has been observed that delay fault tests can produce a fault coverage as high as 92% compared to 29% produced by stuck-at tests, for the same set of faults for a BiCMOS inverter. The implications of this dominant failure mode are discussed and a gate level design-for-testability (DFT) scheme is presented
Keywords :
BiCMOS integrated circuits; design for testability; integrated circuit testing; integrated logic circuits; logic CAD; logic gates; BiCMOS inverter; BiCMOS logic gate; DFT; circuit level faults; delay fault tests; dominant failure mode; fault coverage; gate level design-for-testability; multiple paths; output node; short faults; stuck-at tests; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Design for testability; Inverters; Logic circuits; Logic testing;
Conference_Titel :
Design Automation, 1992. Proceedings., [3rd] European Conference on
Conference_Location :
Brussels
Print_ISBN :
0-8186-2645-3
DOI :
10.1109/EDAC.1992.205996
