DocumentCode
3100680
Title
WDM-enabled optical RAM architectures for ultra-fast, low-power optical cache memories
Author
Kanellos, G.T. ; Alexoudi, T. ; Fitsios, D. ; Vagionas, Christos ; Maniotis, P. ; Papaioannou, S. ; Miliou, A. ; Pleros, N.
Author_Institution
Inf. Technol. Inst., Center for Res. & Technol. Hellas, Thessaloniki, Greece
fYear
2013
fDate
23-27 June 2013
Firstpage
1
Lastpage
4
Abstract
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work on optical RAM cell configurations exploiting silicon-based integrated switching and latching elements with SOAs serving as the active devices. We review both their experimental and underlying theoretical framework and proceed with the demonstration of new optical cache architectural paradigms enabled by the introduction of WDM principles in the storage area. The higher than 40GHz optical RAM cell operational speeds and the WDM-enabled cache architectures comprise two major factors towards realizing ultra-fast and low-power CPU-memory communication.
Keywords
cache storage; elemental semiconductors; flip-flops; high-speed optical techniques; information retrieval; integrated optoelectronics; low-power electronics; memory architecture; microprocessor chips; optical interconnections; random-access storage; semiconductor optical amplifiers; wavelength division multiplexing; CPU-memory communication; SOA; WDM; active device; electronic RAM clock frequency; frequency 40 GHz; information retrieval; information storage; latching element; low power optical cache memory; memory wall problem; optical RAM architecture; optical RAM cell configuration; optically interconnected CPU memory architecture; processor memory performance gap; ps-scale memory access; semiconductor optical amplifier; silicon-based integrated switching; ultra fast optical cache memory; Computer architecture; Integrated optics; Logic gates; Optical filters; Optical interferometry; Random access memory; Wavelength division multiplexing; access gate (AG); column decoder (CD); optical RAM; optical memory; row decoder; semiconductor optical amplifier (SOA); silicon technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Transparent Optical Networks (ICTON), 2013 15th International Conference on
Conference_Location
Cartagena
ISSN
2161-2056
Type
conf
DOI
10.1109/ICTON.2013.6603029
Filename
6603029
Link To Document