Title :
A new decoding solution for the asynchronous sigma delta modulator
Author :
Wei Chen ; Papavassiliou, Christos
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
Abstract :
A new type of low power decoding circuit for asynchronous sigma delta modulators is presented. The circuit implements a special coarse-fine time-to-digital converter to quantize the square wave produced by asynchronous sigma delta modulators, and converts the duty cycle to a digital output. The time-to-digital converter operates asynchronously by utilizing vernier delay lines. The purpose of this circuit is to achieve a high resolution with a low frequency sampling clock, which is suitable for the ultra-low power applications. The proposed circuit is designed in 0.35um. Spectre simulations, show an 11-bit resolution is realized with 0.06LSB integral non-linearity and 0.04LSB differential non-linearity. The simulated power consumption is below16uW from a dual 0.6 V supply voltage.
Keywords :
asynchronous circuits; circuit simulation; clocks; decoding; delay lines; low-power electronics; sigma-delta modulation; time-digital conversion; Spectre simulation; asynchronous sigma delta modulator; coarse-fine time-to-digital converter; differential non-linearity; integral nonlinearity; low frequency sampling clock; low power decoding circuit; power consumption; size 0.35 mum; square wave quantization; ultralow power application; vernier delay line; voltage 0.6 V; word length 11 bit; Clocks; Decoding; Delay lines; Delays; Frequency modulation; Sigma-delta modulation; asynchronous sigma delta modulator (ASDM); time-to-digital converter (TDC); vernier delay line (VDL);
Conference_Titel :
Ph.D. Research in Microelectronics and Electronics (PRIME), 2013 9th Conference on
Conference_Location :
Villach
Print_ISBN :
978-1-4673-4580-4
DOI :
10.1109/PRIME.2013.6603115