VLSI implementation of a fast radix-4 SRT division

Author

Wey, Chin-Long ; Wang, Cheng-Ping

Author_Institution

Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA

Volume

1

fYear

1996

fDate

18-21 Aug 1996

Firstpage

65

Abstract

The design of fast divider is an important issue in high speed computing. This paper presents a fast radix-4 SRT division architecture. Instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, the two-step process does not influence the overall speed. Since the decision making circuits can be implemented with simple gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit takes 29l ns for a double precision division (56 bits for fraction part) where the 2 μm SCMOS technology in MAGIC was used for layout

Keywords

CMOS digital integrated circuits; VLSI; dividing circuits; integrated circuit design; 2 micron; 291 ns; MAGIC; SCMOS technology; VLSI implementation; division architecture; double precision division; fast radix-4 SRT division; gate structures; partial remainders; quotient digit; Arithmetic; Circuits; Computer architecture; Decision making; Equations; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.594031

Filename

594031