VLSI implementation of a fast radix-4 SRT division

The design of fast divider is an important issue in high speed computing. This paper presents a fast radix-4 SRT division architecture. Instead of finding the correct quotient digit, an estimated quotient digit is first speculated. The speculated quotient digit is used to simultaneously compute the two possible partial remainders for the next step while the quotient digit is being corrected. Thus, the two-step process does not influence the overall speed. Since the decision making circuits can be implemented with simple gate structures, the proposed divider offers fast speed operation. Based on the physical layout, the circuit takes 29l ns for a double precision division (56 bits for fraction part) where the 2 μm SCMOS technology in MAGIC was used for layout