Title :
A parallel pipelined DSP processor core
Author :
Aikens, Valentine C., II ; Delgado-Frias, José G. ; Pechanek, Gerald G. ; Vassiliadis, Stamatis
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
Abstract :
In this paper a novel high performance processor is presented along with its applicability to digital signal processing. The generic sum of product processor organization contains three major sections: parallel, reduction, and multifunction generator. Each of these sections works in a pipelined fashion providing extremely high performance. We have studied a number of digital signal processing algorithms and mapped them onto the proposed processor. We report the mapping of three of the most widely used algorithms: convolution, discrete Fourier transform, and discrete cosine transform. In order to evaluate the potential impact of the processor, we have included a performance comparison with other digital signal processing machines. The proposed processor performs extremely well using a small amount of hardware
Keywords :
convolution; digital signal processing chips; discrete Fourier transforms; discrete cosine transforms; parallel architectures; pipeline processing; convolution; digital signal processing algorithms; discrete Fourier transform; discrete cosine transform; generic sum of product; multifunction generator; parallel pipelined DSP processor core; processor organization; Convolution; Delay; Digital signal processing; Discrete Fourier transforms; Feedback; Hardware; Microelectronics; Multiplexing; Parallel processing; Signal processing algorithms;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594039