Fast sampled-data wavelet transform CMOS VLSI implementation

This paper presents the VLSI CMOS implementation of a one-dimensional Fast Sampled-Data Wavelet Transform (FSDWT) circuit and its inverse based on subband dyadic decomposition using Quadrature Mirror Filter banks (QMF). The originality in this approach lies in the use of novel analog building blocks such as analog tapped delay lines, analog four-quadrant multipliers, and current addition in order to build the analysis and synthesis stages of a programmable QMF. This paper presents the basic architecture, as well a a transistor level computer simulation of a four-stage Finite Impulse Response (FIR) filter based QHF which decomposes a test transient (non-stationary) signal into its Daubechies-4 wavelet coefficients; and then by using them synthesizes the original signal. Important VLSI features for this particular approach are the following: area efficiency, speed (5 MHz sampling rate), and low power consumption