• DocumentCode
    3105355
  • Title

    On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

  • Author

    Fujita, Masahiro ; Matsunaga, Yusuke ; Kakuda, Taeko

  • Author_Institution
    Fujitsu Lab. Ltd., Kawasaki, Japan
  • fYear
    1991
  • fDate
    25-28 Feb 1991
  • Firstpage
    50
  • Lastpage
    54
  • Abstract
    Develops multi-level logic minimization programs using binary decision diagram (BDD). The authors present variable ordering methods of BDD. The variable ordering algorithm for two-level circuits is based on cover patterns and selects most binate variables first, and the one for multi-level circuits is based on depth first traverse of circuits. In both cases, the acquired variable orderings are optimized by exchanging a variable with its neighbor in the ordering
  • Keywords
    decision theory; logic design; minimisation of switching nets; binary decision diagram; binary decision diagrams; binate variables; depth first traverse; logic minimization programs; multi-level logic synthesis; two-level circuits; variable ordering methods; Binary decision diagrams; Boolean functions; Circuit synthesis; Circuit testing; Data structures; Logic circuits; Logic functions; Logic testing; Minimization; Network topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation. EDAC., Proceedings of the European Conference on
  • Conference_Location
    Amsterdam
  • Type

    conf

  • DOI
    10.1109/EDAC.1991.206358
  • Filename
    206358