Title :
Delay estimation for CMOS functional cells
Author_Institution :
Microelectron. Center, Tech. Univ. of Denmark, Lyngby, Denmark
Abstract :
Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment
Keywords :
CMOS integrated circuits; circuit layout CAD; delays; integrated logic circuits; CELLO; CMOS functional cells; RC tree network model; cell compiler; delay estimation; performance driven layout synthesis; silicon compiler environment; topological changes; worst case analysis; Algorithm design and analysis; Boolean functions; Circuit synthesis; Circuit topology; Delay estimation; Microelectronics; Network synthesis; Performance analysis; Semiconductor device modeling; Silicon compiler;
Conference_Titel :
Design Automation. EDAC., Proceedings of the European Conference on
Conference_Location :
Amsterdam
DOI :
10.1109/EDAC.1991.206369
