Electrical modelling of lossy on-chip multilevel interconnecting lines

Author

Dimopoulos, K.Z. ; Avaritsiotis, J.N. ; White, S.J.

Author_Institution

Dept. of Electr. Eng., Nat. Tech. Univ. of Athens, Athens, Greece

fYear

1991

fDate

25-28 Feb 1991

Firstpage

106

Lastpage

110

Abstract

A self contained method for the electrical modelling of lossy 3-D multilevel interconnections has been developed. The method allows for the generation of a multiple coupled line model, compatible with SPICE-like CAD programs, from the interconnection line constants and parasitic coupling parameters which are computed by the so-called method of moments. The proposed method can be used for the analysis of coupled line systems with linear or nonlinear/time varying terminators, as well as for the study of the pulse propagation characteristics in high-speed ICs. Numerical results are presented for 3-D parallel and galvanically separated crossed planar lines

Keywords

VLSI; metallisation; transmission line theory; 3D parallel planar lines; 3D separated crossed planar lines; SPICE-like CAD programs; analysis of coupled line systems; crossed planar lines; electrical modelling; high-speed ICs; interconnection line constants; lossy 3-D multilevel interconnections; method of moments; multiple coupled line model; on-chip multilevel interconnecting lines; parasitic coupling parameters; pulse propagation characteristics; Bit rate; Dielectrics; Geometry; Integrated circuit interconnections; Moment methods; Nonhomogeneous media; Packaging; Solid modeling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation. EDAC., Proceedings of the European Conference on

Conference_Location

Amsterdam

Type

conf

DOI

10.1109/EDAC.1991.206370

Filename

206370