• DocumentCode
    3106477
  • Title

    Breaking correlation to improve testability

  • Author

    Ockunzzi, Kelly ; Papachristou, Chris

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    75
  • Lastpage
    80
  • Abstract
    A BIST-based design-for-test method targeting correlation in circuit behaviors is proposed. Correlation introduced by reconvergent fanout and conditional statements is considered. Testability problems caused by correlation are described and behavioral modification techniques to implicitly break the correlation are presented. An analysis and insertion scheme is proposed that systematically identifies testability problems in a circuit and modifies the circuit to resolve these problems. Experimental results from five examples show that this scheme improves the fault coverage of circuits with correlated signals while minimizing the impact on area and critical delay
  • Keywords
    built-in self test; delays; design for testability; fault location; integrated circuit testing; logic testing; BIST-based design-for-test method; behavioral modification techniques; conditional statements; correlated signals; critical delay; fault coverage; reconvergent fanout; testability problems; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Electrical fault detection; Fault detection; Hardware; Job shop scheduling; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 19th IEEE Proceedings on. VTS 2001
  • Conference_Location
    Marina Del Rey, CA
  • Print_ISBN
    0-7695-1122-8
  • Type

    conf

  • DOI
    10.1109/VTS.2001.923421
  • Filename
    923421