Design of low power and high speed ripple carry adder using modified feedthrough logic

This paper presents the design of a low power and high performance circuit using a new CMOS domino logic family called feedthrough logic (FTL). Feedthrogh logic improves the performance of arithmetic circuit by performing partial evaluation in its computational block before its input signals are valid. FTL improves the speed of arithmetic circuits along with more power consumption. The proposed modified FTL achieves both reductions in average power consumption along with the improvement in speed at the cost of area. A long chain of inverter (10-stage) and a 16-bit ripple carry adder is designed by the proposed modified feedthrough logic. Then a comparison analysis has been carried out by simulating the logic circuits in 0.18 um technology. The simulation shows that the proposed modified circuit reduces the dynamic power consumption up to 45% along with a improvement in speed by a factor of 1.65.