Average leakage current estimation of CMOS logic circuits

In a product engineering environment there is a need to know quickly the average standby current of an IC for various combinations of power supply and temperature. We present two techniques to do this estimation without resorting to involved simulations. We use a bottom-up methodology that propagates the effect of process variations to higher levels of abstraction. In one approach, the leakage current of any given circuit is computed by adding up individual cell currents indexed from a statistically characterized library of standard cells. The second method is based on empirical formulae derived from results of the standard cell library characterization. In this approach the total leakage current is estimated without the need for any simulations and using only the circuit´s equivalent cell-count. We present here the statistical foundation of our approach as well as experimental results on actual ICs