A high speed and high precision 64/spl times/33 crosspoint switch IC

A monolithic 2.125GB/s per port 64/spl times/33 crosspoint switch IC has been designed, fabricated, and tested. A 0.6 um enhancement/depletion, recessed gate GaAs process was chosen for this product, which offers high speed devices with low power dissipation. The design used SCFL (Source Coupled FET Logic) standard cells for the switch matrix. All the data path signals use standard differential PECL input and output levels to maintain precision pulse width characteristics. The control signals, are in TTL levels. The high speed data inputs are DC biased allowing AC coupled operation. The switch offers non-blocking programming, and can be configured prior to enabling the outputs for synchronous reprogramming and operation from a single +5V supply.